The present invention relates to a semiconductor integrated circuit and a testing method therefor.
In recent years, various methods for recovering defective memory cells that exist in a semiconductor memory have been developed. One such method tests a semiconductor memory to detect a defective memory cell, and substitutes the detected defective memory cell with a redundancy memory cell in order to enable the memory to function as a normal semiconductor memory.
More specifically, the method first tests all memory cells in order to detect a defective memory cell. Then, by storing an address of this defective memory cell into a fuse or the like, the method substitutes the defective memory cell with a redundancy memory cell.
Finally, the method once again tests all memory cells to perform a retest on whether the substitution has been successfully performed. This method has a problem in that a long testing time is required, since all memory cells are subjected to testing even during the retest.
The following is a patent document related to rescue of defective memory cells.
Japanese Patent Laid-Open No. 2002-93190